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fn817 rev.6.00 page 1 of 17 aug 1, 2005 fn817 rev.6.00 aug 1, 2005 ca3130, ca3130a 15mhz, bimos operational amplifie r with mosfet input/cmos outpu t datasheet ca3130a and ca3130 are op amps that combine the advantage of both cmos and bipolar transistors. gate-protected p-channel mosfe t (pmos) transistors are used in the input circuit t o provide very-high-input impedance, very-low-input curr ent, and except ional speed performance. the use of pmos transistors in the input stage results in common-mode input -voltage capability down to 0.5v below the negative-suppl y terminal, an important attribute in single- supply applications. a cmos transistor-pair, cap able of swinging the output voltage to within 10mv of either supply-voltage terminal (at very high values of load impedance), is employed as the output circuit. the ca3130 series circuits operate at supply voltages ranging from 5v to 16v, ( ? 2.5v to ? 8v). they can be phase compensated with a single ex ternal capacitor, and have terminals for adjustment of of fset voltage for applications requiring offset-null capability. terminal provisions are also made to permit strobing of the output stage. ? the ca3130a offers superior input characteristics over those of the ca3130. features ? mosfet input stage provides: - very high z i = 1.5 t ? (1.5 x 10 12 ? ) (typ) - very low i i . . . . . . . . . . . . . 5pa (typ) at 15v operation . . . . . . . . . . . . . . . . . . . . . = 2pa (typ) at 5v op eration ? ideal for single-supply applications ? common-mode input-voltage range includes negative supply rail; input terminals can be swung 0.5v below negative supply rail ? cmos output stage permits signal swing to either (or both) supply rails ? pb-free plus anneal available (rohs compliant) applications ? ground-referenced si ngle supply amplifiers ? fast sample-hold amplifiers ? long-duration timers/monostables ? high-input-impedance comparators (ideal interface with digital cmos) ? high-input-impedance wideband amplifiers ? voltage followers (e.g. fo llower for single-supply d/a converter) ? voltage regulators (permits control of output voltage down to 0v) ? peak detectors ? single-supply full-wave precision rectifiers ? photo-diode sensor amplifiers pinout ca3130, ca3130a (pdip, soic) top view ordering information part no. (brand) temp. range ( o c) package pkg. dwg. # ca3130ae -55 to 125 8 ld pdip e8.3 ca3130am (3130a) -55 to 125 8 ld soic m8.15 ca3130am96 (3130a) -55 to 125 8 ld soic tape and reel m8.15 ca3130amz (3130az) (note) -55 to 125 8 ld soic (pb-free) m8.15 ca3130amz96 (3130az) (note) -55 to 125 8 ld soic tape and reel (pb-free) m8.15 CA3130E -55 to 125 8 ld pdip e8.3 CA3130Ez (note) -55 to 125 8 ld pdip* (pb-free) e8.3 ca3130m (3130) -55 to 125 8 ld soic m8.15 ca3130m96 (3130) -55 to 125 8 ld soic tape and reel m8.15 ca3130mz (3130mz) (note) -55 to 125 8 ld soic (pb-free) m8.15 ca3130mz96 (3130mz) -55 to 125 8 ld soic tape and reel (pb-free) m8.15 *pb-free pdips can be used for through hole wave solder process ing only. they are not intended for use in reflow solder processing applications. note: intersil pb-free plus anneal products employ special pb-fr ee material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-f ree soldering operations. intersil pb-free products are msl classified at pb- free peak reflow temperatures that meet or exceed the pb-free requirements of ip c/jedec j std-020. offset inv. non-inv. v- 1 2 3 4 8 7 6 5 strobe v+ output offset - + null input input null
ca3130, ca3130a fn817 rev.6.00 page 2 of 17 aug 1, 2005 absolute maximum ratings thermal information dc supply voltage (between v+ and v- terminals) . . . . . . . . . .16v differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8v dc input voltage . . . . . . . . . . . . . . . . . . . . . . (v + +8v) to (v- -0.5v) input-terminal current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1ma output short-circuit duration (note 1). . . . . . . . . . . . . . . . indefinite operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . -50 o c to 125 o c thermal resistance (typical, note 2) ? ja ( o c/w) ? jc ( o c/w) pdip package* . . . . . . . . . . . . . . . . . . 115 n/a soic package . . . . . . . . . . . . . . . . . . . 160 n/a maximum junction temperat ure (plastic package) . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c (soic - lead tips only) *pb-free pdips can be used for through hole wave solder process - ing only. they are not intended for use in reflow solder proces sing applications. caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. short circuit may be applied to ground or to either supply. 2. ? ja is measured with the component mounted on an evaluation pc boa rd in free air. electrical specifications t a = 25 o c, v+ = 15v, v- = 0v, unless otherwise specified parameter symbol test conditions ca3130 ca3130a units min typ max min typ max input offset voltage |v io |v s = ? 7.5v - 8 15 - 2 5 mv input offset voltage temperature drift ? v io / ? t - 10 - - 10 - ? v/ o c input offset current |i io |v s = ? 7.5v - 0.5 30 - 0.5 20 pa input current i i v s = ? 7.5v - 5 50 - 5 30 pa large-signal voltage gain a ol v o = 10v p-p r l = 2k ? 50 320 - 50 320 - kv/v 94 110 - 94 110 - db common-mode rejection ratio cmrr 70 90 - 80 90 - db common-mode input voltage range v icr 0 -0.5 to 12 10 0 -0.5 to 12 10 v power-supply rejection ratio ? v io / ? v s v s = ? 7.5v - 32 320 - 32 150 ? v/v maximum output voltage v om +r l = 2k ? 12 13.3 - 12 13.3 - v v om -r l = 2k ? - 0.002 0.01 - 0.002 0.01 v v om +r l = ? 14.99 15 - 14.99 15 - v v om -r l = ? - 0 0.01 - 0 0.01 v maximum output current i om + (source) at v o = 0v 122245122245ma i om - (sink) at v o = 15v 12 20 45 12 20 45 ma supply current i+ v o = 7.5v, r l = ? - 10 15 - 10 15 ma i+ v o = 0v, r l = ? -23-23ma
ca3130, ca3130a fn817 rev.6.00 page 3 of 17 aug 1, 2005 electrical specifications typical values intended only for design guidance, v supply = 7.5v, t a = 25 o c unless otherwise specified parameter symbol test conditions ca3130, ca3130a units input offset voltage adjustment range 10k ? across terminals 4 and 5 or 4 and 1 ? 22 mv input resistance r i 1.5 t ? input capacitance c i f = 1mhz 4.3 pf equivalent input noise voltage e n bw = 0.2mhz, r s = 1m ? (note 3) 23 ? v open loop unity gain crossover frequency (for unity gain stability ? 47pf required.) f t c c = 0 15 mhz c c = 47pf 4 mhz slew rate: sr c c = 0 30 v/ ? s open loop closed loop c c = 56pf 10 v/ ? s transient response: c c = 56pf, c l = 25pf, r l = 2k ? (voltage follower) 0.09 ? s rise time t r overshoot os 10 % settling time (to <0.1%, v in = 4v p-p )t s 1.2 ? s note: 3. although a 1m ? source is used for this test, th e equivalent input noise remai ns constant for values of r s up to 10m ?? electrical specifications typical values intended only for design guidance, v+ = 5v, v- = 0v, t a = 25 o c unless otherwise specified (note 4) parameter symbol test conditions ca3130 ca3130a units input offset voltage v io 82mv input offset current i io 0.1 0.1 pa input current i i 22pa common-mode rejection ratio cmrr 80 90 db large-signal voltage gain a ol v o = 4v p-p , r l = 5k ? 100 100 kv/v 100 100 db common-mode input voltage range v icr 0 to 2.8 0 to 2.8 v supply current i+ v o = 5v, r l = ? 300 300 ? a v o = 2.5v, r l = ? 500 500 ? a power supply rejection ratio ? v io / ? v+ 200 200 ? v/v note: 4. operation at 5v is not recommended for temperatures below 25 o c.
ca3130, ca3130a fn817 rev.6.00 page 4 of 17 aug 1, 2005 schematic diagram application information circuit description figure 1 is a block diagram of the ca3130 series cmos operational amplifiers. the in put terminals may be operated down to 0.5v below the negative s upply rail, and the output can be swung very close to ei ther supply rail in many applications. consequently, the ca3130 series circuits are ideal for single-supply operat ion. three class a amplifier stages, having the individual gain capability and current consumption shown in figure 1, provide the total gain of the ca3130. a biasing circuit provid es two potentials for common use in the first and second stages. terminal 8 can be used both for phase compensation and to strobe the output stage into qui escence. when terminal 8 is tied to the negative supply rail (terminal 4) by mechanical or electrical means, the output potential at terminal 6 essentiall y rises to the posi tive supply-rail potentia l at terminal 7. this condition of essentially zero cur rent drain in the output stage under the strobed off condition can only be achieved when the ohmic load resistance presen ted to the ampl ifier is very high (e.g.,when the am plifier output is us ed to drive cmos digital circuits in co mparator applications). input stage the circuit of the ca3130 is show n in the schematic diagram. it consists of a differential-inpu t stage using pmos field-effect transistors (q 6 , q 7 ) working into a mir ror-pair of bipolar transistors (q 9 , q 10 ) functioning as load resistors together with resistors r 3 through r 6 . the mirror-pair transistors also function as a differential-to- single-ended converter to provide base drive to the second- stage bipolar transistor (q 11 ). offset nulling, when desired, can be effected by connecting a 100,000 ? potentiometer across terminals 1 and 5 and the potenti ometer slider arm to terminal 4. 3 2 1 8 4 6 7 q 1 q 2 q 4 d 1 d 2 d 3 d 4 q 3 q 5 d 5 d 6 d 7 d 8 q 9 q 10 q 6 q 7 5 z 1 8.3v input stage r 3 1k ? r 4 1k ? r 6 1k ? r 5 1k ? non-inv. input inv.-input + - r 1 40k ? 5k ? r 2 bias circuit current source for current source load for q 11 q 6 and q 7 v+ output output stage q 8 q 12 v- q 11 second stage offset null compensation strobing (note 5) note: 5. diodes d 5 through d 8 provide gate-oxide protection for mosfet input stage.
ca3130, ca3130a fn817 rev.6.00 page 5 of 17 aug 1, 2005 cascade-connected pmos transisto rs q2, q4 are the constant- current source for the input st age. the biasing circuit for the constant-current source is subsequently described. the small diodes d 5 through d 8 provide gate-oxide protection against high-voltage transients, i ncluding static electricity d uring handling for q 6 and q 7 . second-stage most of the voltage gain in t he ca3130 is pro vided by the second amplifier stage, consisting of bipolar transistor q 11 and its cascade-connected load res istance provided by pmos transistors q 3 and q 5 . the source of bias potentials for these pmos transistors is subsequen tly described. miller effect compensation (roll-off) is accomplished by simply connecting a small capacitor between terminals 1 and 8. a 47pf capacitor provides sufficient compensat ion for stable unity-gain operation in most applications. bias-source circuit at total supply voltages, somew hat above 8.3v, resistor r 2 and zener diode z 1 serve to establish a volt age of 8.3v across the series-connected circuit, c onsisting of resistor r 1 , diodes d 1 through d 4 , and pmos transistor q 1 . a tap at the junction of resistor r 1 and diode d 4 provides a gate-bias potential of about 4.5v for pmos transistors q 4 and q 5 with respect to terminal 7. a potential of about 2.2v is dev eloped across diode-connected pmos transistor q 1 with respect to terminal 7 to provide gate bias for pmos transistors q 2 and q 3 . it should be noted that q 1 is mirror-connected (s ee note 8) to both q 2 and q 3 . since transistors q 1 , q 2 , q 3 are designed to be identical, the approximately 200 ? a current in q 1 establishes a similar current in q 2 and q 3 as constant current source s for both the first and second amplifier stages, respectively. at total supply voltages somew hat less than 8.3v, zener diode z 1 becomes nonconductive and the potential, developed across series-connected r 1 , d 1 -d 4 , and q 1 , varies directly with variations in supply volta ge. consequently, the gate bias for q 4 , q 5 and q 2 , q 3 varies in accordance with supply- voltage variations. thi s variation results in deterioration of the power-supply-rejection ratio (ps rr) at total supply voltages below 8.3v. operation at total supply voltages below about 4.5v results in seriou sly degraded performance. output stage the output stage consis ts of a drain-loaded inverting amplifier using cmos transistors operati ng in the class a mode. when operating into very high resis tance loads, the output can be swung within millivolts of eith er supply rail. because the outp ut stage is a drain-loaded amplif ier, its gain is dependent upon the load impedance. the transfer characteristics of the output stage for a load returned to the negative supply r ail are shown in figure 2. typical op amp lo ads are readily driven by the output stage. because large-sign al excursions are non-linear, requiring feedback for good wave form reproduction, transient delays may be encountered. a s a voltage follower, the amplifier can achieve 0.01% a ccuracy levels, including the negative supply rail. note: 8. for general information on the ch aracteristics of cmos transi stor- pairs in linear-circuit applicati ons, see file number 619, data sheet on ca3600e cmos transistor array. 3 2 7 4 8 1 5 6 bias ckt. compensation (when required) a v ? 5x a v ? a v ? 6000x 30x input + - 200 ? a 200 ? a 1.35ma 8ma 0ma v+ output v- strobe c c offset null ca3130 (note 7) (note 5) notes: 6. total supply voltage (for indicated voltage gains) = 15v with input terminals biased so that termi nal 6 potential is +7.5v above terminal 4. 7. total supply voltage (for indicated voltage gains) = 15v with output terminal driven to either supply rail. figure 1. block diagram of the ca3130 series 22.5 gate voltage (terminals 4 and 8) (v) output voltage (terminals 4 and 8) (v) 17.5 20 12.5 15 10 7.5 2.5 5 0 2.5 7.5 5 10 15 12.5 17.5 0 supply voltage: v+ = 15, v- = 0v t a = 25 o c load resistance = 5k ? 500 ? 1k ? 2k ? figure 2. voltage transfer characteristics of cmos output stage
ca3130, ca3130a fn817 rev.6.00 page 6 of 17 aug 1, 2005 input current variation with common mode input voltage as shown in the table of electri cal specifications, the input current for the ca3130 series op amps is typically 5pa at ta = 25oc when terminals 2 and 3 are at a common-mode potential of +7.5v wit h respect to negative s upply terminal 4. figure 3 contains data showing the variation of input current as a function of common-mode input voltage at ta = 25oc. these data show that circuit designers can advantageously exploit these characteristics to design circuits which typically requir e an input current of less than 1pa , provided the common-mode input voltage does not exceed 2 v. as previously noted, the input current is essentially the result of the leakage current through the gate-protection di odes in the input circuit and, therefore, a functio n of the applied volt age. although the fini te resistance of the glass terminal-t o-case insulator of the metal can package also contributes an increment of leakage current, there are useful com pensating factors. because the gate- protection network functions as if it is connected to terminal 4 potential, and the metal can case of the ca3130 is also internally tied to terminal 4, i nput terminal 3 is essentially guarded from spurious leakage currents. offset nulling offset-voltage nulling is usual ly accomplished with a 100,000 ? potentiometer connected acro ss terminals 1 and 5 and with the potentiometer slider arm co nnected to terminal 4. a fine offset-null adjustment usually c an be effected with the slider arm positioned in the mid-point of the potentiom eters total range. input-current variation with temperature the input current of the ca3130 series circuits is typically 5p a at 25oc. the major portion of t his input current is due to leakage current through the gate-p rotective diodes in the input circuit. as with any semiconductor-junction device, including o p amps with a junction-fet inpu t stage, the leakage current approximately doubles for every 10oc increase in temperature. figure 4 provides data on the typical variation of input bias current as a functi on of temperature in the ca3130. in applications requiring the low est practical input current an d incremental increases in current because of warm-up effects, it is suggested that an appropr iate heat sink be used with the ca3130. in addition, when sink ing or sourcing significant output current the chip temperature increases, causing an increase in the inpu t current. in such cases, heat-sinking can also very markedly reduce and stabilize input current variations. input offset voltage (v io ) variation with dc bias and device operating life it is well known that the charac teristics of a mosfet device can change slightly w hen a dc gate-source bias potential is applied to the device for e xtended time periods. the magnitude of the change is incr eased at high temperatures. users of the ca3130 should be alert to the possible impacts of this effect if the application of the device involves extended operation at high temperatures with a significant differential dc bias voltage applied across terminals 2 and 3. figure 5 shows typical data pertinent to shifts in offset voltage encountered with ca3130 devices (me tal can package) dur ing life testing. at lower temperatures (metal c an and plastic), for example at 85oc, this change in voltage is considerably less. in typical linear applications wher e the differential voltage is small and symmetrical, these incremental changes are of about the same magnitude as those encountered in an operational amplifier employing a bipolar transis tor input stage. the 2vdc differential voltage example represents conditions when the amplifier output stage is togg led, e.g., as in comparator applications. 10 7.5 5 2.5 0 -101234567 input current (pa) input voltage (v) t a = 25 o c 3 2 7 4 8 6 pa v in ca3130 15v to 5v 0v to -10v v+ v- figure 3. input current vs common-mode voltage v s = ? 7.5v 4000 1000 100 10 1 -80 -60 -40 -20 0 20 40 60 80 100 120 140 input current (pa) temperature ( o c) figure 4. input current vs temperature
ca3130, ca3130a fn817 rev.6.00 page 7 of 17 aug 1, 2005 o power-supply considerations because the ca3130 is very useful in single-supply applications, it is pertinent to review some considerations relating to power-supply current consumption under both single-and dual-supply servic e. figures 6a and 6b show the ca3130 connected for both dual-and single-supply operation. dual-supply operation: when the output voltage at terminal 6 is 0v, the currents supplied by the two power supplies are equal. when the gate terminals of q 8 and q 12 are driven increasingly positive with respect to ground, current flow through q 12 (from the negative supply) to the load is increased and current flow through q 8 (from the positive supply) decreases correspondingly. when the gate terminals of q 8 and q 12 are driven increasingly ne gative with respect to ground, current flow through q 8 is increased and current flow through q 12 is decreased accordingly. single-supply operation: initially, let it be assumed that the value of r l is very high (or disconnected), and that the input-terminal bias (terminals 2 and 3) is su ch that the output terminal (no. 6) voltage is at v+/2, i.e., the voltage drops across q 8 and q 12 are of equal magnitude. figure 20 s hows typical quiescent supply- current vs supply-voltage for the ca3130 operated under these conditions. since the output sta ge is operating as a class a amplifier, the supply-current will remain constant under dynami c operating conditions as long as t he transistors are operated in the linear portion of their voltag e-transfer characteristics (s ee figure 2). if either q 8 or q 12 are swung out of their linear regions toward cut-off (a non -linear region), there will be a corresponding reductio n in supply-current. i n the extreme case, e.g., with terminal 8 swung down to ground potential (or tied t o ground), nmos transistor q 12 is completely cut off and the supply-current to series- connected transistors q 8 , q 12 goes essentially to zero. the two pr eceding stages in the ca3130, however, continue to draw modest supply-current (see the lower curve in figure 20) even though t he output stage is strobed off . figure 6a shows a dual-supply arrangement for the output stage that can also be strobed off, assuming r l = ? by pulling the potential of terminal 8 down to that of terminal 4. let it now be assumed that a loa d-resistance of nominal value (e.g., 2k ? ) is connected between terminal 6 and ground in the circuit of figure 6b. let it be assumed again that the input- terminal bias (terminals 2 and 3) is such that the output terminal (no. 6) voltage is at v +/2. since pmos transistor q 8 must now supply quiescent current to both r l and transistor q 12 , it should be apparent that under these conditions the supply-current must increase a s an inverse function of the r l magnitude. figure 22 shows the voltage-drop across pmos transistor q 8 as a function of load current at several supply voltages. figure 2 shows the voltage-transfer characteristics o f the output stage for several values of load resistance. wideband noise from the standpoint of low-noise performance considerations, the use of the ca3130 is most advantageous in applications where in the source resistance of the input signal is on the order of 1m ? or more. in this case, the total input-referred noise voltage is typically only 23 ? v when the test-circuit amplifier of figure 7 is operat ed at a total sup ply voltage of 15v. this value of total input-referred noise remains essential ly constant, even though the value of source resistance is raised by an order of magnitude. this ch aracteristic is due to the fac t that reactance of the input capac itance becomes a significant factor in shunting the source resistance. it should be noted, however, that for values of s ource resistance very much greater than 1m ? , the total noise vo ltage generated can be dominated by the thermal noise contributions of both the feedback and source resistors. figure 5. typical incremental offset-voltage shift vs operating life figure 6a. dual power supply operation figure 6b. single pow er supply operation figure 6. ca3130 output stage in dual and single power supply operation t a = 125 o c for to-5 packages 7 6 5 4 3 2 1 0 500 1000 1500 2000 2500 3000 3500 4000 offset voltage shift (mv) time (hours) differential dc voltage (across terminals 2 and 3) = 0v output voltage = v+ / 2 differential dc voltage (across terminals 2 and 3) = 2v output stage toggled 0 3 2 8 4 7 6 r l q 8 q 12 ca3130 + - v+ v- 3 2 8 4 7 6 r l q 8 q 12 ca3130 + - v+
ca3130, ca3130a fn817 rev.6.00 page 8 of 17 aug 1, 2005 typical applications voltage followers operational amplifiers with very high input resistances, like t he ca3130, are particularly suited to service as voltage followers . figure 8 shows the circuit of a classical voltage follower, together with pert inent waveforms using t he ca3130 in a split- supply configuration. a voltage follower, operated from a single supply, is shown in figure 9, together with related wa veforms. this follower circui t is linear over a wide dynami c range, as illustrated by the reproduction of the output wavef orm in figure 9a with input- signal ramping. the waveforms in figure 9b show that the follower does not lose its inpu t-to-output phase-sense, even though the input is being swung 7.5v below ground potential. this unique characteristic is an important attribute in both operational amplifier and compar ator applicatio ns. figure 9b also shows the manner in which the cmos output stage permits the output signal to swing down to the negative supply- rail potential (i.e., ground in the case shown). the digital-to - analog converter (dac) circuit, described later, illustrates th e practical use of the ca3130 in a single-supply voltage-follower application. 9-bit cmos dac a typical circuit of a 9-bit dig ital-to-analog converter (dac) is shown in figure 10 . this system combines the concepts of multiple-switch cmo s lcs, a low-cost l adder network of discrete metal-oxide-film r esistors, a ca3130 op amp connected as a follower, a nd an inexpensive monolithic regulator in a simple single power-supply arrangement. an additional feature of the dac is that it is readily interfaced with cmos input logic, e.g., 10v logic levels are used in the circui t of figure 10. the circuit uses an r/2r vol tage-ladder network, with the output potential obtained direct ly by terminating the ladder arms at either the positive o r the negative power-supply terminal. each cd4007a contains three inverters, each inverter functioning as a si ngle-pole double-throw switch to terminate an arm of the r/2r network at either the positive or negative power-supply terminal. the resistor ladder is an assembly of 1% tolerance metal-ox ide film resistors. the five arms requiring the highest accuracy are assembled with series and parallel combinations of 806,000 ? resistors from the same manufacturing lot. a single 15v supply provides a positive bus for the ca3130 follower amplifier and feeds the ca3085 voltage regulator. a scale-adjust function is pro vided by the regulator output control, set to a nom inal 10v level in this system. the line- voltage regulation (approximately 0.2%) permits a 9-bit accuracy to be maintained with variations of several volts in t he supply. the flexibility afforded by t he cmos building blocks simplifies the design of dac s ystems tailored to particular needs. single-supply, absolute-value, ideal full-wave rectifier the absolute-value circuit us ing the ca3130 is shown in figure 11. during posit ive excursions, the input signal is fed through the feedback netwo rk directly to the output. simultaneously, the positive excu rsion of the in put signal also drives the output terminal (no. 6) of the inverting amplifier i n a negative-going excursion such that the 1n914 diode effectively disconnects the amplifier from the signal path. during a negative-going excursion of t he input signal, the ca3130 functions as a normal inverti ng amplifier with a gain equal to - r 2 /r 1 . when the equality of the two equations shown in figure 11 is satisfied, the full-wa ve output is symmetrical. peak detectors peak-detector circuits are easily implemented with the ca3130, as illustrated in figure 12 for both the peak-positive and the peak-negative circuit. it should be noted that with large-signal inputs, the bandwidth of the peak-negative circuit is much less than that of the peak-positive circuit. the second stage of the ca3130 limits th e bandwidth in this case. negative-going output-signal e xcursion requires a positive- going signal excursion at t he collector of transistor q 11 , which is loaded by the intrinsic capacitance of the associated circui try in this mode. on the other hand, during a negative-going signal excursion at the collector of q 11 , the transistor functions in an active pull-down mode so that the intrinsic capacitance can be discharged more expeditiously. 3 2 1 8 4 7 6 + - r s 1m ? 47pf -7.5v 0.01 ? f +7.5v 0.01 ? f noise voltage output 30.1k ? 1k ? bw (-3db) = 200khz total noise voltage (referred to input) = 23 ? v (typ) figure 7. test-circuit amplifier (30-db gain) used for wideband noise measurements
ca3130, ca3130a fn817 rev.6.00 page 9 of 17 aug 1, 2005 3 2 1 8 4 7 6 + - 10k ? c c = 56pf -7.5v 0.01 ? f +7.5v 0.01 ? f 2k ? 2k ? bw (-3db) = 4mhz sr = 10v/ ? s 25pf 0.1 ? f top trace: otpt center trace: inpt figure 8a. small-signal response (50mv/div., 200ns/div.) top trace: otpt sinal; 2v/div., 5 ? s/div. center trace: difference signal; 5mv/div., 5 ? s/div. bottom trace: input signal; 2v/div., 5 ? s/div. figure 8b. input-output dif ference signal showing settling time (measurement made with tektronix 7a13 differential amplifier) figure 8. split supply voltage follower with associated waveforms 3 2 8 1 4 7 6 + - 10k ? 56pf offset +15v 0.01 ? f 2k ? 0.1 ? f 5 adjust 100k ? figure 9a. output waveform with input signal ramping (2v/div., 500 ? s/div.) top trace: otpt; 5v/div., 200 ? s/div. bottom trace: input signal; 5v/div., 200 ? s/div. figure 9b. output waveform with ground reference sine-wave input figure 9. single supply voltage follower with associated waveforms. (e.g., for use in single-supply d/a converter; see figure 9 in an6080)
ca3130, ca3130a fn817 rev.6.00 page 10 of 17 aug 1, 2005 figure 10. 9-bit dac using cmos digital switches and ca3130 figure 11. single supply, absolute value, ideal full-wave rectif ier with associated waveforms 6 3 10 10 3 6 4 8 3 6 7 9 4 10 2 3 13 8 12 12 1 5 8 13 13 1 12 8 5 14 11 2 6 5 1 7 7 1 6 8 4 3 2 10v logic inputs +10.010v lsb 987 654 321 msb 806k 1% paralleled resistors +15v voltage follower ca3130 output load 100k offset null 56pf 2k 0.1 ? f regulated voltage adj 22.1k 1% 1k 3.83k 1% 0.001 ? f ca3085 voltage regulator +15v 2 ? f 25v + - +10.010v cd4007a switches cd4007a switches 402k 1% 200k 1% 100k 1% 806k 1% 806k 1% 806k 1% 750k 1% 806k 1% 806k 1% 806k 1% 806k 1% (2) (4) (8) 806k 1% + - 62 bit 1 2 3 4 5 6 - 9 required ratio-match standard ? 0.1% ? 0.2% ? 0.4% ? 0.8% ? 1% abs note: all resistances are in ohms. cd4007a switches 1 5 10k 2 3 4 6 8 1 5 7 r 2 2k ? +15v 0.01 ? f 1n914 r 3 5.1k ? peak adjust 2k ? 100k ? offset adjust 20pf ca3130 r 1 4k ? + - 20v p-p input: bw(-3db) = 230khz, dc output (avg) = 3.2v 1v p-p input: bw(-3db) = 130khz, dc output (avg) = 160mv gain = r 2 r 1 ------ - = x = r 3 r 1 + r 2 + r 3 ------------------------------------- r 3 = r 1 x + x 2 1 - x ------------------ ?? ?? for x = 0.5: 2k ? 4k ? ----------- - = r 2 r 1 ------ - r 3 = 4k ? 0.75 0.5 ----------- ?? ?? = 6k ? top trace: output signal; 2v/div. bottom trace: input signal; 10v/div. time base on both traces: 0.2ms/div. 0v 0v
ca3130, ca3130a fn817 rev.6.00 page 11 of 17 aug 1, 2005 figure 12a. peak positive detector circuit figure 12b. peak negati ve detector circuit figure 12. peak-detector circuits figure 13. voltage regulator circuit (0v to 13v at 40ma) 3 2 6 4 7 ca3130 +7.5v 0.01 ? f +dc output 5 ? f + - 100 k ? 1n914 0.01 ? f -7.5v 2k ? 10k ? + - 6v p-p input; bw (-3db) = 1.3mhz 0.3v p-p input; bw (-3db) = 240khz 3 2 6 4 7 ca3130 +7.5v 0.01 ? f -dc output 5 ? f + - 100 k ? 1n914 0.01 ? f -7.5v 2k ? 10k ? + - 6v p-p input; bw (-3db) = 360khz 0.3v p-p input; bw (-3db) = 320khz 6 3 2 1 8 7 4 ca3086 current limit adj 3 ? r 2 1k ? q 5 13 14 12 q 1 q 2 q 3 q 4 10 7 3 4 2 6 9 11815 390 ? 1k ? 20k ? + - 5 ? f 25v 56pf error amplifier ca3130 30k ? 100k ? ic1 0.01 voltage adjust 50k ? r 1 14 13 q 5 12 62k ? ic 3 output 0 to 13v at 40ma + - 0.01 ? f +20v input 2.2k ? + - 25 ? f ic 2 ca3086 10 11 1, 2 q 4 q 1 8, 7 5 q 3 q 2 6 4 regulation (no load to full load): <0.01% input regulation: 0.02%/v hum and noise output: <25 ? v up to 100khz + - + - 1k ? 9 ? f 3
ca3130, ca3130a fn817 rev.6.00 page 12 of 17 aug 1, 2005 error-amplifier in re gulated-power supplies the ca3130 is an ideal choice for error-amplifier service in regulated power supplies since it can function as an error- amplifier when the regulated ou tput voltage is required to approach zero. figure 13 shows the schematic diagram of a 40ma power supply capable of p roviding regulated output voltage by continuous adjustment over the range from 0v to 13v. q 3 and q 4 in lc 2 (a ca3086 transistor-array lc) function as zeners to provide suppl y-voltage for the ca3130 comparator (ic 1 ). q 1 , q 2 , and q 5 in ic 2 are configured as a low impedance, temperatur e-compensated source of adjustable reference voltage for the error amplifier. transisto rs q 1 , q 2 , q 3 , and q 4 in lc 3 (another ca3086 transistor-array lc) are connected in parallel as the series-pass element. transistor q 5 in lc 3 functions as a current-limiting device by diverting base drive from the series-pass transistors, in accordance with the adj ustment of resistor r 2 . figure 14 contains the schematic diagram of a regulated power-supply capable of providi ng regulated output voltage by continuous adjustment over t he range from 0 .1v to 50v and currents up to 1a. the error amplifier (lc 1 ) and circuitry associated with lc 2 function as previously described, although the output of lc 1 is boosted by a di screte transistor (q 4 ) to provide adequate base drive for the darlington-connected series-pass transistors q 1 , q 2 . transistor q 3 functions in the previously described cu rrent-limiting circuit. multivibrators the exceptionally high input resistance presented by the ca3130 is an attracti ve feature for multiv ibrator circuit desig n because it permits the use of t iming circuits with high r/c ratios. the circuit diagram o f a pulse generator (astable multivibrator), with provisions for indepe ndent control of the on and off periods, is show n in figure 15. resistors r 1 and r 2 are used to bias the ca3130 to the mid-point of the supply- voltage and r 3 is the feedback resistor . the pulse r epetition rate is selected by positioning s 1 to the desired position and the rate remains esse ntially constant when the resistors which determine on-period and off-period are adjusted. function generator figure 16 contains a schematic diagram of a function generator using the ca3130 in the integrator and threshold detector functions. this circuit generates a triangular or square-wave output that can be swept over a 1,000,000:1 range (0.1hz to 100khz) by means of a single control, r 1 . a voltage-control input is also available fo r remote sweep-control. the heart of the frequency- determining system is an operational-transconductance-am plifier (ota) (see note 10), lc 1 , operated as a voltage-cont rolled current-source. the figure 14. voltage regulator circuit (0.1v to 50v at 1a) 6 2 3 1 8 7 4 4.3k ? 1 ? + - 43k ? 100 ? f error amplifier ic 1 voltage adjust 14 13 100 ? f +55v input 2.2k ? + - ic 2 ca3086 10, 11 q 4 q 1 q 2 6 regulation (no load to full load): <0.005% input regulation: 0.01%/v hum and noise output: <250 ? v rms up to 100khz + - + - ca3130 + - + - 1w 3.3k ? 1w 5 ? f 9 8, 7 q 3 1, 2 3 5 4 1k ? 62k ? q 5 12 10k ? q 2 q 1 50k ? q 3 1k ? 2n3055 2n2102 current limit adjust 2n5294 2n2102 q 4 1000pf 10k ? 8.2k ? output: 0.1 to 50v at 1a
ca3130, ca3130a fn817 rev.6.00 page 13 of 17 aug 1, 2005 output, i o , is a current applied directly to the integrating capacitor, c 1 , in the feedback loop of the integrator lc 2 , using a ca3130, to provide the triangular-wave output. potentiometer r 2 is used to adjust the circuit fo r slope symmetry of positive- going and negative-going signal excursions. another ca3130, ic 3 , is used as a controlled switch to set the excursion limits of the triangul ar output from the integrator circuit. capacitor c 2 is a peaking adjustm ent to optimize the high-frequency square-wave pe rformance of the circuit. potentiometer r 3 is adjustable to perfect the amplitude symmetry of the square-wave out put signals. output from the threshold detector is fed back via resistor r 4 to the input of lc 1 so as to toggle the current s ource from plus to minus in generating the linear triangular wave. operation with output-stage power-booster the current-sourcing and-sinking capability of the ca3130 output stage is easily supplemented to provide power-boost capability. in the circuit of figure 17, three cmos transistor- pairs in a single ca 3600e (see note 12) lc array are shown parallel connected with the output stage in the ca3130. in the class a mode of ca3600e shown , a typical device consumes 20ma of supply current at 15v operation. this arrangement boosts the current-handling capability of the ca3130 output stage by about 2.5x. the amplifier circuit in figure 17 employs feedback to establis h a closed-loop gain of 48db. the typical large-signal bandwidth (-3db) is 50khz. note: 9. see file number 619 for technical information. 7 4 6 3 2 r 1 100k ? r 2 100k ? r 3 100k ? on-period adjust 1m ? 2k ? 2k ? off-period adjust 1m ? +15v 0.01 ? f output 2k ? 0.001 ? f 0.01 ? f 0.1 ? f 1 ? f s 1 ca3130 + - figure 15. pulse generator (astable multivibrator) with provisions for independent control of on and off periods frequency range: position of s 1 0.001 ? f 0.01 ? f 0.1 ? f 1 ? f pulse period 4 ? s to 1ms 40 ? s to 10ms 0.4ms to 100ms 4ms to 1s note: 10. see file number 475 and an6668 for technical information. figure 16. function generator (frequency can be varied 1,000,000 /1 with a single control) 6 3 2 1 4 7 5 6 2 3 4 7 8 1 5 4 6 7 3 2 r 4 270k ? +7.5v voltage-controlled current source ic 1 3k ? 3k ? 10m ? +7.5v r 2 100k ? slope symmetry adjust voltage controlled input -7.5v 10k ? 10k ? r 1 -7.5v frequency adjust (100khz max) -7.5v +7.5v i o ic 2 +7.5v c 1 100pf integrator -7.5v 56pf ca3130 + - ca3080a + - 39k ? 3 - 30pf c 2 adjust high - freq. detector threshold 150k ? ic 3 +7.5v ca3130 + - r 3 100k ? amplitude symmetry adjust 22k ? -7.5v (note 10)
ca3130, ca3130a fn817 rev.6.00 page 14 of 17 aug 1, 2005 notes: 11. transistors q p1 , q p2 , q p3 and q n1 , q n2 , q n3 are parallel connected with q 8 and q 12 , respectively, of the ca3130. 12. see file number 619. figure 17. cmos transistor array (ca3600e) connected as power bo oster in the output stage of the ca3130 8 7 3 2 +15v 2k ? ca3130 + - 4 10 3 6 4 9 7 6 14 750k ? 1 ? f 2 11 13 1 12 5 8 1 ? f 1m ? 0.01 ? f 510k ? 500 ? f q p3 q n1 q n2 q n3 q p2 q p1 ca3600e a v(cl) = 48db large signal bw (-3 db) = 50khz r l = 100 ? (p o = 150mw at thd = 10%) (note 12) input typical performance curves figure 18. open loop gain vs temp erature figure 19. open-loop resp onse load resistance = 2k ? 150 140 130 120 110 100 90 80 -100 -50 0 50 100 open loop voltage gain (db) temperature ( o c) supply voltage: v+ = 15v; v- = 0 t a = 25 o c ? ol 3 2 1 1 2 3 4 4 aol 1 - c l = 9pf, c c = 0pf, r l = ?? 2 - c l = 30pf, c c = 15pf, r l = 2k ? 3 - c l = 30pf, c c = 47pf, r l = 2k ? 4 - c l = 30pf, c c = 150pf, r l = 2k ? 120 100 80 60 40 20 0 open loop voltage gain (db) -100 -200 -300 open loop phase (degrees) 10 2 10 3 10 4 10 5 10 6 10 7 10 8 frequency (hz) 10 1
ca3130, ca3130a fn817 rev.6.00 page 15 of 17 aug 1, 2005 figure 20. quiescent su pply current vs supply voltage figure 21. quiescent supply current vs supply voltage figure 22. voltage across pmos output transistor (q 8 ) vs load current figure 23. voltage across nmos output transistor (q 12 ) vs load current typical performance curves (continued) load resistance = ? t a = 25 o c v- = 0 output voltage balanced = v+/2 output voltage high = v+ or low = v- 17.5 12.5 10 7.5 5 2.5 0 6 8 10 12 14 16 18 total supply voltage (v) quiescent supply current (ma) 4 output voltage = v+/2 v- = 0 14 12 10 8 6 4 2 0246 810121416 quiescent supply current (ma) total supply voltage (v) t a = -55 o c 25 o c 125 o c 0 50 10 1 0.1 0.01 0.001 0.001 0.01 0.1 1.0 10 100 magnitude of load current (ma) voltage drop acro ss pmos output stage transistor (v) 15v 10v negative supply voltage = 0v t a = 25 o c positive supply voltage = 5v negative supply voltage = 0v t a = 25 o c 50 10 1 0.1 0.01 0.001 0.001 0.01 0.1 1 10 100 magnitude of load current (ma) voltage drop across nmos output stage transistor (v) 15v 10v positive supply voltage = 5v
ca3130, ca3130a fn817 rev.6.00 page 16 of 17 aug 1, 2005 dual-in-line plastic packages (pdip) c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a 1 -a- 0.010 (0.25) c a m bs notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions , the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the mo series symbol list in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protru- sions. mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be per- pendicular to datum . 7. e b and e c are measured at the lead tips with the leads uncon- strained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- e8.3 (jedec ms-001-ba issue d) 8 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.210 - 5.33 4 a1 0.015 - 0.39 - 4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8, 10 c 0.008 0.014 0.204 0.355 - d 0.355 0.400 9.01 10.16 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n8 89 rev. 0 12/93
fn817 rev.6.00 page 17 of 17 aug 1, 2005 ca3130, ca3130a intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas ll c 1998-2005. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. small outline plastic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m ? notes: 1. symbols are defined in the mo series symbol list in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension d does not include mold flash, protrusions or gat e burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm ( 0.006 inch) per side. 4. dimension e does not include interlead flash or protrusions . inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. l is the length of terminal for soldering to a substrate. 7. n is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width b, as measured 0.36mm (0.014 inch) or greate r above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millime ter. converted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 ? 0 8 0 8 - rev. 1 6/05

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